1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to field effect transistors (FETs) having structures in which the resistance of interconnections to FETs is decreased and substantially coplanar surface structures. The present invention further relates to a method of manufacturing such devices.
2. Description of the Background Art
When the present invention is applied to a dynamic random access memory (referred to as DRAM hereinafter) having memory cells each having a stacked capacitor structure, the most preferable effect is obtained. Therefore, description is made on a DRAM having memory cells of a stacked capacitor structure. The DRAM has been already well known. FIG. 3 is a block diagram showing one example of an entire structure of such a conventional DRAM.
Referring to FIG. 3, the DRAM comprises a memory cell array 100 including a plurality of memory cells each serving as a storing portion, a row decoder 200 and a column decoder 300 each connected to an address buffer for selecting addresses, and an input/output interface portion comprising sense amplifiers connected to an input/output circuit. The plurality of memory cells each serving as a storing portion are provided in a matrix of a plurality of rows and columns. Each of the memory cells is connected to a corresponding word line connected to the row decoder 200 and a corresponding bit line connected to the column decoder 300. The memory cells constitute the memory cell array 100. A memory cell is selected by a single word line and a single bit line selected by the row decoder 200 and the column decoder 300 upon receipt of externally applied row and column address signals. Data is written to the selected memory cell or the data stored in the memory cell is read out. Reading/writing of this data is commanded by a read/write control signal applied to a control circuit.
Data is stored in the N (=n.times.m)-bit memory cell array 100. Address information concerning a memory cell from/to which reading/writing is performed are stored in the row and column address buffers, so that an m-bit memory cell is coupled to the sense amplifiers through bit lines by selecting a particular word line (one word line out of n word lines) by the row decoder 200. Then, one sense amplifier out of the sense amplifiers is coupled to the input/output circuit by selecting a particular bit line (one bit line out of m bit lines) by the column decoder 300, so that reading or writing is performed according to the command of the control circuit.
FIG. 4 is a diagram showing an equivalent circuit of one memory cell 30 in the DRAM shown for explaining an operation for reading/writing data to/from memory cells. In FIG. 4, the memory cell 30 comprises a set of a field effect transistor Q and a capacitor Cs. The field effect transistor Q has its gate electrode connected to a word line 40, one source-drain electrode connected to one electrode of the capacitor Cs, and another source-drain electrode connected to a bit line 50. At the time of writing data, a predetermined voltage is applied to the word line 40 so that the field effect transistor Q is rendered conductive, whereby charges applied to the bit line 50 are stored in the capacitor Cs. On the other hand, at the time of reading out data, a predetermined voltage is applied to the word line 40 so that the field effect transistor Q is rendered conductive, whereby the charges stored in the capacitor Cs are extracted through the bit line 50.
FIG. 5 is a partial plan view showing planar arrangement of a peripheral circuit including a decoder portion or the like other than a memory cell array region in the conventional DRAM. FIG. 5 shows three field effect transistors T1, T2 and T3. Each of the transistors comprises a transfer gate 4 and N-type impurity diffused regions 60a and 60b to be a source/drain region arranged on both sides of the transfer gate 4. The transfer gate 4 to be a gate electrode constituting each of the field effect transistors is formed in accordance with a predetermined interconnection pattern. In addition, contact holes 14a and 14b are respectively formed in the N-type impurity diffused regions 60a and 60b to be a source/drain region constituting each of the transistors so as to electrically contact with the regions. In FIG. 5, the contact hole 14b formed in the transistor T1, the contact hole 14b formed in the transistor T2 and the contact hole 14a formed in the transistor T3 are provided to be aligned in a lateral direction. The reason is that the contact holes are aligned in a constant direction irrespective of different sizes of impurity diffused regions respectively constituting the transistors T1, T2 and T3 in order to efficiently form an interconnection pattern or the like in the design of a semiconductor device. Therefore, margins differ in the impurity diffused regions respectively constituting the transistors T1, T2 and T3, so that respective distances between the contact holes and the transfer gate, i.e., contact-gate spacing D1, D2 and D3 differ from each other
FIG. 6A is a partially sectional view showing a cross section taken along a line VI--VI shown in FIG. 5. FIG. 7A is a partially sectional view showing a cross section taken along a line VII--VII shown in FIG. 5. Referring to FIGS. 6A and 7A, description is made on a structure of a field effect transistor having different contact-gate spacing (D1, D2).
Thick isolation oxide films 2 are formed spaced apart from each other on a P-type silicon substrate 1 to isolate field effect transistors. An N channel MOS transistor is formed in a region surrounded by the isolation oxide films 2. The N channel MOS transistor comprises a transfer gate 4 and N-type impurity diffused regions 60a and 60b to be a source/drain region. The transfer gate 4 is formed over the silicon substrate 1 through a transfer gate oxide film 3, and a sidewall insulating film 7 is formed on both sidewalls thereof. An interlayer insulating film 12 is formed so as to cover this N channel MOS transistor. Contact holes 14a and 14b are respectively formed on the interlayer insulating film 12 so as to reach the surfaces of N-type impurity diffused regions 60a and 60b to be a source/drain region. Interconnection layers 20a and 20b are respectively provided so as to electrically contact with the N-type impurity diffused regions 60a and 60b through the contact holes 14a and 14b.
It is assumed that in each of the N channel MOS transistors T1 and T2 shown in FIGS. 5, 6A and 7A, gate lengths L1 and L2 and gate widths W1 and W2 respectively take the same value. In addition, it is assumed that junction depths x.sub.j of the N-type impurity diffused regions take the same value. Under such conditions, respective drain current-drain voltage characteristics, as characteristics of the field effect transistor, in the transistors T1 and T2 are compared with each other.
FIG. 6B is a graph showing drain current (Id)-drain voltage (Vd) characteristics of the N channel MOS graph transistor T1 shown in FIG. 6A, and FIG. 7B is a graph showing drain current-drain voltage characteristics of the N channel MOS transistor T2 shown in FIG. 7A. According to the graphs, in the transistor T1 having small contact-gate spacing (D1), the slope of the rise of the drain current is steep and an angle .alpha.1 is small. On the other hand, in the transistor T2 having large contact-gate spacing (D2), the slope of the rise of the drain current is gentle and an angle .alpha.2 is large. In addition, the transistor T2 having large contact-gate spacing, the value of the drain current at the same gate voltage (V.sub.G) is smaller. From the foregoing, it can be understood that a transistor having a large interconnection resistance to the drain/source region and a transistor having a small interconnection resistance thereto are formed depending on contact-gate spacing. Thus, characteristics of a transistor such as the operation speed varies between the transistors having the same gate length and gate width.
Furthermore, as the semiconductor device is miniaturized, N-type impurity diffused regions serving as a source/drain region are formed such that the junction depths x.sub.j thereof are small. This means that a source-drain resistance (resistance of an impurity diffused region) becomes large. Thus, if and when the source-drain resistance becomes large, the variation in the above described contact-gate spacing greatly affects characteristics of a transistor.
In order to solve the above described problem, a field effect transistor having a structure in which a polysilicon (polycrystalline silicon) layer is stacked on the surfaces of impurity diffused regions to be a source/drain region is disclosed in Japanese Patent Laying-Open No. 62-154784/(1987). FIG. 8 shows a cross-sectional structure of this field effect transistor.
Referring to FIG. 10, thick isolation oxide films 2 are formed spaced apart from each other on a P-type silicon substrate 1 to achieve isolation. An N channel MOS transistor is formed in a region surrounded by the isolation oxide films 2. This N channel MOS transistor comprises a transfer gate 4 formed over the silicon substrate 1 through a transfer gate oxide film 3 and N-type impurity diffused regions 60a and 60b to be a source/drain region. An insulating oxide film 5 is formed on the transfer gate 4, and a sidewall insulating film 7 is formed on sidewalls thereof. A polysilicon layer 22 is formed on the surfaces of the N-type impurity diffused regions 60a and 60b.
In the N channel MOS transistor having such a structure, the polysilicon layer 22 electrically contacts with the N-type impurity diffused regions 60a and 6Ob. Therefore, contact-gate spacing D3 becomes short. In addition, interconnection layers 20a and 20b can be provided in a desired position on the polysilicon layer 22. More specifically, the contact-gate spacing D3 is uniformly decreased in each of transistors, so that a source-drain interconnection having decreased resistance is provided. However, the polysilicon layer 22 in this structure is formed using etchback techniques, so that it is difficult t make the thickness thereof uniform between the transistors. Therefore, it is difficult to uniformly decrease the resistance of the source-drain interconnection between the transistors.
FIGS. 9A to 9C are partial sectional views showing, in this order, the method for forming the polysilicon layer 22 by using etch back technique in the structure shown in FIG. 8. The etch back technique is one of the methods for making the layer coplanar. Referring to FIG. 9A, the polysilicon layer 22 is formed on the entire surface, and a photoresist film 23 is applied thick on the polysilicon layer 22. Thereafter, as shown in FIG. 9B, the photoresist film 23 and the polysilicon layer 22 are removed so as to expose the surface of the insulating oxide film 5 with the speed of etching the photoresist film 23 and the polysilicon layer 22 made equal to each other, by using, for example, RIE (reactive ion etching) technique. Thereafter, as shown in FIG. 9C, the photoresist film 23 is removed by turning the same to ash in oxide plasma. When the polysilicon layer 22 is made coplanar in this manner, the thickness t.sub.2 of the polysilicon layer 22 on the isolating oxide film 2 is made smaller than the thickness t.sub.1 of the polysilicon layer 22 on the N type impurity diffused regions 60a and 60b. Therefore, it is difficult to make uniform the thickness of the polysilicon layer 22. Accordingly, the resistance between the polysilicon layer 22 and the interconnection layers formed thereon is not uniform.
On the other hand, in a memory cell array region in the DRAM shown in FIG. 3, a more highly integrated field effect transistor is formed, as compared with that in a region where a peripheral circuit is formed shown in FIG. 5. FIG. 10 is a partially sectional view showing a structure of a memory cell having such a highly integrated field effect transistor and having a stacked capacitor structure. Referring to FIG. 8, description is made on the structure of the memory cell.
Thick isolation oxide films 2 are formed spaced apart from each other on a major surface of a P type silicon substrate 1 to isolate memory cells. Memory cells are formed in a region surrounded by the isolation oxide films 2. Each of the memory cells comprises an N channel MOS transistor and a capacitor. The N channel MOS transistor comprises a transfer gate 4 shared with a word line and an N-type impurity diffused region. The transfer gate 4 is formed over the silicon substrate 1 through a transfer gate oxide film 3. The N-type impurity diffused region to be a source/drain region has an LDD (lightly doped drain) structure comprising N-type impurity diffused regions 6a and 6b of low concentration and N-type impurity diffused regions 8a and 8b of high concentration. A sidewall insulating film 7 is formed on both sidewalls of the transfer gate 4.
On the other hand, a capacitor is formed so as to be connected to the N channel MOS transistor. The capacitor comprises a storage node 9, a capacitor gate oxide film 10 formed to cover the storage node 9, and a cell plate 11 formed to cover the capacitor gate oxide film 10 The storage node 9 is formed so as to electrically contact with one set of the N-type impurity diffused regions 6a and 8a constituting the N channel MOS transistor In the above described manner, each of the memory cells comprises an N channel MOS transistor and a capacitor.
In order to send information charges to each of the memory cells, a bit line 50 is formed so as to electrically contact with the other set of the N-type impurity diffused regions 6b and 8b constituting the N channel MOS transistor. This bit line 50 is formed through a contact hole 13 formed on an interlayer insulating film 12 formed above each of the memory cells
In the memory cell having the above described stacked capacitor structure, a distance a between sidewalls of the contact hole 13 becomes smaller and smaller as the memory cell is miniaturized. Therefore, the ratio of a distance b between the upper surface of the interlayer insulating film 12 covering each of the memory cells and the surface of the silicon substrate 1 to the distance a between the sidewalls of the contact hole 13 becomes larger and larger as the memory cell is miniaturized. More specifically, as a memory cell region is miniaturized, a stepped structure has a larger aspect ratio. This makes it difficult to uniformly pattern the bit line 50 formed so as to cover the interlayer insulating film 12. More specifically, it becomes difficult to make the stepped structure coplanar For example, as shown in FIG. 10, an interconnection layer such as the bit line formed to electrically contact with the impurity diffused region is formed such that the thickness thereof becomes small on the sidewalls of the contact hole. Therefore, electrical disconnection may occur. In addition, the junction depth xj of the impurity diffused region becomes small as the memory cell is miniaturized, and thickness of the interconnection layer formed so as to electrically contact with the impurity diffused region becomes small so that the resistance thereof is increased.
As described above, in the peripheral circuit portions of a DRAM, respective transistors are arranged with the efficiency in design given priority. Meanwhile, in the memory cell area of the DRAM, the transistors are arranged with the degree of integration given priority Consequently, there have been the following drawbacks
For example, in the conventional DRAM, characteristics of a field effect transistor constituting a peripheral circuit or the like varies even if it has the same gate length and gate width according to the relative relation between the source-drain resistance (resistance of an impurity diffused region) and the contact-gate spacing.
On the other hand, in a semiconductor device including a highly integrated field effect transistor, the cross-sectional structure thereof has a large aspect ratio due to high integration density of a memory cell in, for example, a region where a memory cell is formed (referred to as memory cell forming region hereinafter) in the DRAM, so that it becomes difficult to make the semiconductor device coplanar.
Meanwhile, a structure in which a tungsten layer is selectively formed in a source/drain region to reduce the resistance of a source-drain interconnection is disclosed in an article by A. Nishiyama, entitled "Two Step Tungsten Selective CVD for High Speed CMOS Device Applications", Toshiba VLSIR. Center 1988 IE.sup.3 [VLSI SYMPOSIUM], pp. 97-98. In this article, an interconnection structure, whose resistance is decreased, to a source/drain region is disclosed. However, this structure can not solve a problem of making coplanar in a miniaturized field effect transistor.